1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a method of forming a field effect transistor having a channel length less than a minimum resolvable feature of the photolithography apparatus.
2. Description of the Relevant Art
The operating characteristics of a transistor fabricated with standard metal-oxide-semiconductor (MOS) integrated circuit techniques are a function of the transistor's dimensions. In particular, the transistor's source-to-drain current (I.sub.ds) is proportional to the ratio of the transistor's width (W) to the transistor's length (L). For a given transistor width W and a given biasing condition (e.g. V.sub.G =3V, V.sub.D =3V, and V.sub.S =0V), I.sub.ds is maximized by minimizing the transistor length L. Minimizing transistor channel length improves the speed of integrated circuits, which comprise a large number of individual transistors, because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from an device operation standpoint. In addition, minimizing the transistor length L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases and, with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon.
The main limitation of minimum device size in a conventional transistor fabrication process is the resolution of the optical lithography printing system. In an optical lithography printing system, radiation is directed from an illumination source through a patterned mask and onto a photoresist layer. The patterned mask transmits the illumination source radiation onto selected areas of the photoresist layer to reproduce the mask pattern in the photoresist layer. Resolution in optical lithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of diffraction effects, there is a minimum distance beyond which even a geometrically perfect lens cannot resolve two points. In other words, when two points are less than a minimum distance from each other, the two points cannot be resolved by the lithography system. The diffraction patterns associated with each point overlap each other to such an extent that the two points cannot be effectively differentiated. The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleigh's criterion criteria defines two images as being resolvable when the intensity between them drops to 80% of the image intensity. This criterion is satisfied when 2nd=0.61.lambda./NA, where 2d is the separation distance of the two images, .lambda. is the wavelength of the energy source, and NA is the numerical aperture of the lens.
Commercially available optical photolithography machines are typically equipped with mercury vapor lamps as the illumination source. The characteristic energy spectrum of a mercury vapor lamp contains several distinct peaks in the 300 nm to 450 nm wavelength range. These peaks are commonly referred to by their industry designations. The peak associated with a wavelength of .about.436 nm is designated the "G-line," the .about.405 nm peak the "H-line," and the .about.370 nm peak the "I-line." Photolithography aligners are similarly designated such that it is common to speak of "G-line aligners." The minimum feature size resolvable by a G-line aligner is greater than the minimum feature size of an I-line aligner because of the longer G-line wavelength.
As process technologies approach and surpass the resolvable limits of G-line and I-line aligners, semiconductor manufacturers are typically forced to implement alternative photolithography techniques to achieve adequate resolution of the minimum features. Unfortunately, the conventional alternatives involve abandoning or substantially modifying the existing photolithography equipment at a prohibitive cost. Many wafer fabrication facilities, for example, have extensive capital investment in I-line aligners. To adequately resolve features in the deep sub-micron range (i.e. &lt;0.5 .mu.m), it is typically necessary to upgrade these aligners or abandon the optical alignment equipment entirely and replace it with advanced lithography equipment including e-beam or x-ray lithography. The cost associated with replacing or upgrading photolithography equipment can be staggering. In addition to the capital required to purchase and install the improved equipment, there are extensive costs associated with qualifying the new equipment for production worthiness and training production and maintenance personnel in the operation and care of the new equipment.
In addition, conventional transistor fabrication processes, in which the transistor gate is formed above the semiconductor substrate, result in a non-planar surface upon which subsequent processing layers must be fabricated. The non-planar surface increases the difficulty of subsequent processing. In particular, photolithography resolution is negatively affected by variations in the thickness of the photoresist layer across non-planar regions or "steps" in the underlying substrate. Photoresist line width variations are common over steps in the underlying substrate primarily due to standing wave effects and light scattering at the steps caused by diffraction and reflection effects.
Therefore, it is highly desirable to design an MOS transistor and a transistor fabrication process in which the transistor channel length is not limited by the capabilities of the photolithography equipment. It would be further desirable if such a process resulted in a substantially planar surface upon which subsequently formed structures could be more easily fabricated.